Dr. Ehsan Atoofian, P.Eng.

Computer Architecture, Quantum Computing, Machine Learning, Graphics Processing Unit, Parallel Programming Models, High-Performance Computing.

Journal Publications

• Sohrab Sajadimanesh, Hanieh Aghaee Rad, Jean Paul Latyr Faye, and Ehsan Atoofian, Inexact Quantum Square Root Circuit for NISQ Devices. To appear in IEEE Access, 2024.
• Mohammad Hafezan and Ehsan Atoofian, Transient Fault Detection in Tensor Cores for Modern GPUs, to appear in the ACM Transactions on Embedded Computing Systems, vol. 23, no. 5, pp. 1-29, 2024.
• Sohrab Sajadimanesh and Ehsan Atoofian: Implementation of a quantum division circuit on noisy intermediate-scale quantum devices using dynamic circuits and approximate computing, Phys. Rev. A, Volume 109, Issue 5, 2024.
• Mohammad Hafezan and Ehsan Atoofian, Improving Energy-efficiency of Capsule Networks on Modern GPUs, IEEE Computer Architecture Letters, Volume 23, Issue 1, 2024.
• Sohrab Sajadimanesh and Ehsan Atoofian: EAM: Ensemble of Approximate Multipliers for Robust DNNs”, Elsevier Journal of Microprocessors and Microsystems-Embedded Hardware Design, Volume 98, April 2023.
• Ehsan Atoofian: PTTS: Power-aware Tensor Cores using Two-Sided Sparsity, Journal of Parallel and Distributed Computing, Volume 173, Pages 70-82, March 2023.
• Ehsan Atoofian, Zayan Shaikh, and Ali Jannesari, “Reducing Energy in GPGPUs through Approximate Trivial Bypassing”, ACM Transactions on Embedded Computing Systems, vol. 20, no. 2, pp. 1-27, 2021.
• Ehsan Atoofian, “Trivial Bypassing in GPGPUs”, IEEE Embedded Systems Letters, Volume 13, Issue 1, March 2021.
• J. Servais and E. Atoofian, “Adaptive Computation Reuse for Energy-Efficient Training of Deep Neural Networks”, ACM Transactions on Embedded Computing Systems, vol. 20, no. 1, pp. 1-24, 2021.
• Ehsan Atoofian, “Approximate Cache in GPGPUs”, ACM Transactions on Embedded Computing Systems, vol. 19, no. 5, pp. 1-22, 2020.
• Milad Mohammadi, Song Han, Ehsan Atoofian, Amirali Baniasadi, Tor M. Aamodt, William J. Dally, “ODBP-PATH: Path-Based On-Demand Dynamic Branch Prediction”, IEEE Transactions on Computers, Volume: 69, Issue: 3, pages 453-465, 2020.
• Yang Xiao, Thireshan Jeyakumaran, Ehsan Atoofian, and Ali Jannesari, “Improving Performance of Transactional Memory through Machine Learning”, Journal of Concurrency and Computation: Practice and Experience, vol. 30, no. 10, pp. 1-15, 2018.
• Ahmad Lashgar, Ehsan Atoofian, Aamirali Baniasadi, “TELEPORT: Hardware/Software Alternative To CUDA Shared Memory Programming”, Journal of Microprocessors and Microsystems, vol. 63, pp. 169-181, 2018.
• Ehsan Atoofian and Sean Rea, “Data-type Specific Cache Compression in GPGPUs”, Journal of Supercomputing, vol. 74, no. 1, pp. 1609-1635, 2018.
• Ehsan Atoofian and Ahsan Saghir, “An Efficient Racetrack Memory for L2 cache in GPGPUs”, International Journal of Computer Systems Science & Engineering, vol. 32, no. 6, pp. 461-471, 2017.
• A. Saghir, E. Atoofian and A. Manzak, “Reducing Power of Memory Hierarchy in General Purpose Graphics Processing Units”, Journal of Low Power Electronics, vol. 13, no. 2, pp. 149-165, 2017.
• A. G. Bavarsad and E. Atoofian, “TurboLock: Increasing Associativity of Lock Table in Transactional Memory”, Journal of Computing, vol. 97, no. 6, pp. 649-661, 2015.
• E. Atoofian, “Adaptive Snoop Granularity and Transactional Snoop Filtering in Hardware Transactional Memory”, IEEE Canadian Journal of Electrical and Computer Engineering, vol. 37, no. 2, pp. 76-85, 2014.
• E. Atoofian, “Boosting Performance of Transactional Memory through O-GEHL Predictors”, Journal on Microprocessors and Microsystems, vol. 38, no. 4, pp. 254-262, 2014.
• E. Atoofian, “Improving performance of software transactional memory through contention locality”, Journal of Supercomputing, vol. 64, no. 2, pp. 527-547, May 2013.
• E. Atoofian, A. Baniasadi, and Y. Coady, "ARV-ALA: Improving Performance of Software Transactional Memory through Adaptive Read and Write Policies”, vol. 78, no. 9, pp. 1559-1571, September 2013.
• E. Atoofian and A. Baniasadi, “Using Supplier Locality in Power-Aware Interconnects and Caches in Chip Multiprocessors”, Journal of Systems Architecture, vol. 54, no. 5, pp. 507-518, October 2007.
• E. Atoofian and A. Baniasadi, “Speculative Trivialization Point Advancing in High Performance Processors”, Journal of Systems Architecture, vol. 53, no. 9, pp. 587-601, September 2007.
• E. Atoofian, A. Baniasadi, and K. Aasaraai, “Exploiting Speculation Cost Prediction in Power-Aware Applications”, Journal of Low Power Electronics, vol. 3, no. 1, pp. 43-53, April 2007.
• E. Atoofian and A. Baniasadi, “Improving Energy-Efficiency in High-Performance Processors by Bypassing Trivial Computations”, IEE Proceedings Computer and Digital Techniques, vol. 153, no. 5, pp. 313-322, September 2006.
• E. Atoofian and Z. Navabi, “A Test Approach for Look-Up Table Based FPGAs”, Journal of Computer Science and Technology, vol. 21, no.1, pp. 141-146, January 2006.

Conference Publications

• Ehsan Atoofian, Hardened-TC: A Low-Cost Reliability Solution for CNNs Run by Modern GPUs, to appear in the 2024 IEEE 37^th International System-on-Chip Conference (SOCC), Germany, 2024.
• Mohammad Hafezan, Reza Jahadi, and Ehsan Atoofian, PCTC: Hardware and Software Co-Design for Pruned Capsule Networks on Tensor Cores, to appear in the International European Conference on Parallel and Distributed Computing, Spain, 2024.
• Mohammad Hafezan and Ehsan Atoofian, Mixed-Precision Architecture for GPU Tensor Cores, in the 23^rd IEEE International Conference on Scalable Computing and Communications, UK, 2023.
• Sohrab Sajadimanesh, Hanieh Aghaee Rad, Jean Paul Latyr Faye, and Ehsan Atoofian, Practical Quantum Activation Function for Quantum Neural Networks, Quantum Days, poster presentation, 2023.
• Sohrab Sajadimanesh, Jean Paul Latyr Faye, and Ehsan Atoofian, "NISQ-Friendly Non-Linear Activation Functions for Quantum Neural Networks", in the Proceedings of 16^th International Conference on Networking, Architecture, and Storage (NAS), 2022, PA, USA.
• Ehsan Atoofian, "Increasing Robustness against Adversarial Attacks through Ensemble of Approximate Multipliers", in the Proceedings of 16^th International Conference on Networking, Architecture, and Storage (NAS), 2022, PA, USA.
• Sohrab Sajadimanesh, Jean Paul Latyr Faye, and Ehsan Atoofian, "Practical approximate quantum multipliers for NISQ devices", in the Proceedings of the 19^th ACM International Conference on Computing Frontiers, pp. 121–130, 2022.
• Ehsan Atoofian, “Sparsity-aware Power Gating for Tensor Cores", In the Proceedings of the IEEE 33^rd International Symposium on Computer Architecture and High Performance Computing, pages 94-103, Belo Horizonte, Brazil, 2021.
• Zayan Shaikh and Ehsan Atoofian, “Approximate Trivial Instructions", in the Proceedings of the ACM International Conference on Computing Frontiers, pp. 1-9, Sicily, Italy, 2020.
• Ehsan Atoofian and Hiroyuki Takizawa, AI-SEPS 2019: Proceedings of the 6th ACM SIGPLAN International Workshop on AI-Inspired and Empirical Methods for Software Engineering on Parallel Computing Systems.
• Ahmad Lashgar, Ehsan Atoofian, and Amirali Baniasadi, “Loop Perforation in OpenACC, to appear in the Proceedings of the 16^th IEEE International Symposium on Parallel and Distributed Processing with Applications, Melbourne, Australia, 2018.
• Sean Rea and Ehsan Atoofian, “Mitigating Critical Path Decompression Latency in Compressed L1 Data Caches via Prefetching”, In the Proceedings of the 2018 IEEE International Parallel & Distributed Processing Symposium Workshop, pp. 1-8, Vancouver, Canada, 2018.
• Ehsan Atoofian, “Temperature-Aware Register Mapping in GPGPUs”, In the Proceedings of the 2016 IEEE Trustcom/BigDataSE/ISPA, pp. 1636-1643, Tianjin, China, 2016.
• Thireshan Jeyakumaran, Ehsan Atoofian, Yang Xiao, Zhen Li, Ali Jannesari, “Improving Performance of Transactional Applications through Adaptive Transactional Memory”, In the Proceedings of the 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, pp. 192-199, Crete, Greece, 2016. 
• Ehsan Atoofian, “Many-Thread Aware Compression in GPGPUs”, In the Proceedings of the 2016 International IEEE Conferences on Scalable Computing and Communications, Toulouse, France, 2016.
• Ehsan Atoofian, “A low power STT-RAM based register file for GPGPUs”, In the Proceedings of the 31st Annual ACM Symposium on Applied Computing, pp. 1732-1738, Pisa, Italy, 2016.
• Ehsan Atoofian, “Compressed L1 data cache and L2 cache in GPGPUs”, In the Proceedings of the 27^th IEEE International Conference on Application-specific Systems, Architectures and Processors, pp. 1-8, London, United Kingdom, 2016.
• E. Atoofian, “Reducing Shift Penalty in Domain Wall Memory through Register Locality”, In the Proceedings of the International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES), Netherlands, 2015.
• E. Atoofian, A. Saghir, “Shift-Aware Racetrack Memory”, In the Proceedings of the 33^rd IEEE International Conference on Computer Design (ICCD), 2015.
• Y. Xiao, Z. Li, E. Atoofian, A. Jannesari, “Automatic Optimization of Software Transactional Memory Through Linear Regression and Decision Tree”, In the Proceedings of 15th International Conference on Algorithms and Architectures for Parallel Processing, pp. 61-73, 2015.
• Ali Jannesari, Siegfried Benkner, Xinghui Zhao, Ehsan Atoofian, Yukionri Sato, Workshop Preview of the 2^nd International Workshop on Software Engineering for Parallel Systems, pp. 95-96, Pittsburgh, PA, USA, October 27, 2015.
• E. Atoofian and A. Manzak, “Power-Aware L1 and L2 Caches for GPGPUs”, In the Proceedings of the European Conference on Parallel Processing, pp. 354-365, Porto, Portugal, 2014.
• K. Chen, E. Atoofian, and A. Manzak, “Improving Power of Cache and Register File through Critical Path Instructions”, In the Proceedings of the 17th Euromicro Conference on Digital System Design, pp. 349 – 355, Verona, Italy, 2014.
• E. Atoofian, “Inter-Warp Prefetching for Register File Caches in GPGPUs”, Workshop on Duplicating, Deconstructing and Debunking, Minneapolis, United States, 2014.
• E. Atoofian, “Acceleration of Software Transactional Memory through Hardware Clock”, In the Proceedings of the Workshop on Manycore Embedded Systems, Minneapolis, pp. 41-47, United States, 2014.
• E. Atoofian, “Reducing Static and Dynamic Power of L1 Data Caches in GPGPUs”, In the Proceedings of the Workshop on High-Performance, Power-Aware Computing, pp. 798-804, Phoenix, United States, 2014.
• A. G. Bavarsad, E. Atoofian, “Read-Write Lock Allocation in Software Transactional Memory”, In the Proceedings of 8th International Conference On P2P, Parallel, Grid, Cloud and Internet Computing (3PGCIC), Compiegne, France, 2013.
• Ehsan Atoofian, “VGTS: Variable Granularity Transactional Snoop”, In the Proceedings of European Conference on Parallel Processing (Euro-Par), pp. 203-214, Aachen, Germany, 2013.
• Ehsan Atoofian, “TxSnoop: Power-Aware Transactional Snoop”, In the Proceedings of the 11^th IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA), Melbourne, Australia, 2013.
• A. G. Bavarsad, E. Atoofian, “Read-Write Lock Allocation in Software Transactional Memory”, In the Proceedings of the 6^th International Workshop on Parallel Programming Models and Systems Software for High-End Computing (P2S2), Lyon, France, 2013. (Held in Conjunction with ICPP’013)
• E. Atoofian, “Consistency Check through O-GEHL Predictors”, In the Proceedings of the 21^st Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP), pp. 218-224, Belfast, North Ireland, 2013.
• A. G. Bavarsad and E. Atoofian, “TRT: Transactional Read Tracking”, In the Proceedings of the thirteen Parallel and Distributed Computing: Applications and Technologies (PDCAT), Beijing, China, 2012.
• E. Atoofian and A. G. Bavarsad, “Maintaining Consistency in Software Transactional Memory through Dynamic Versioning Tuning”, In the Proceedings of 12^th International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP), pp. 40-49, Fukuoka, Japan, 2012.
• E. Atoofian and A. G. Bavarsad, “Speculative Versioning through Perceptron Predictors”, In the Proceedings of the 14^th IEEE International Conference on High Performance Computing and Communications (HPCC), pp. 1125-1130, Liverpool, UK, 2012.
• E. Atoofian and A. G. Bavarsad, “Combining Local and Global Clock for Efficient Concurrency”, In the Second International Workshop on Future Architectural Support for Parallel Programming (FASPP), Portland, OR, USA, 2012. (Held in Conjunction with ISCA’12)
• E. Atoofian and A. G. Bavarsad, “AGC: adaptive global clock in software transactional memory”, In the Proceedings of the 2012 International Workshop on Programming Models and Applications for Multicores and Manycores (PMAM), pp. 11-16, New Orleans, LA, 2012. (Held in Conjunction with PPoPP’12)
• E. Atoofian, “ArTA: Adaptive Granularity in Transactional Applications”, In the Proceedings of the 20^th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP), pp. 74-80, Munich, Germany, 2012.
• E. Atoofian, “Set Associative Lock in Software Transactional Memory”, In the Proceedings of the 2^nd Workshop on Applications for Multi and Many Core Processors (A4MMC), San Jose, California, 2011. (Held in Conjunction with ISCA’11)
• E. Atoofian, “Speculative Contention Avoidance in Software Transactional Memory”, In the Proceedings of the 12^th IEEE International Workshop on Parallel and Distributed Scientific and Engineering Computing (PDSEC), pp. 1417-1423, Anchorage, Alaska, 2011. (Held in Conjunction with IPDPS’11)
• E. Atoofian, A. Baniasadi, and Y. Coady, "Adaptive Read Validation in Time-Based Software Transactional Memory”, In the Proceedings of the 2^nd Workshop on Highly Parallel Processing on a Chip, pp. 28-37, Spain, August 2008.
• E. Atoofian and A. Baniasadi, "Exploiting Program Cyclic Behavior to Reduce Memory Latency in Embedded Processors”, In the Proceedings of the 2008 ACM Symposium on Applied Computing, pp. 1482-1486, Brazil, March 16-20, 2008.
• E. Atoofian, A. Baniasadi, and K. Aasaraai, "Speculative Supplier Identification for Reducing Power of Interconnects in Snoopy Cache Coherence Protocols", In the ACM International Conference on Computing Frontiers, pp. 259-266, Italy, May 7-9, 2007. (Presented by: Ehsan Atoofian)
• K. Aasaraai, A. Baniasadi, and E. Atoofian, "Computational and Storage Power Optimizations for the O-GEHL Branch Predictor", In the ACM International Conference on Computing Frontiers, pp. 105-112, Italy, May 7-9, 2007. (Presented by: Ehsan Atoofian)
• E. Atoofian and A. Baniasadi, "A Power-Aware Prediction-Based Cache Coherence Protocol for Chip Multiprocessors", In the Third Workshop on High-Performance, Power-Aware Computing, pp. 1-8, Long Beach, California, March 2007.
• E. Atoofian, A. Baniasadi and Farzad Khosrow-Khavar, "Using Speculation Cost Predictability in Low-Power Cost-Aware Branch Prediction", Workshop on Complexity-Effective Design, pp. 44-49, Boston, USA, June 2006. (Presented by: Ehsan Atoofian)
• Maged Ghoneima, E. Atoofian, A. Baniasadi, and Yehea Ismail, “Low-Power Prediction Based Data Transfer Architecture”, IEEE Custom Integrated Circuits Conference, September, pp. 313-316, San Jose, California, 2005.
• E. Atoofian and A. Baniasadi, “Improving Energy-Efficiency by Bypassing Trivial Computations”, First Workshop on High-Performance, Power-Aware Computing, Denver, Colorado, April 4, 2005. (Presented by: Ehsan Atoofian)
• E. Atoofian, A. Baniasadi and Nikitas Dimopoulos, “Improving Performance by Speculating Trivializing Operands in Trivial Instructions”, Second Value-Prediction and Value-Based Optimization Workshop, pp.26-31, October 10, Boston, Massachusetts, USA, 2004.
• M. Alisafaee, S. Hatami, E. Atoofian, Z. Navabi, and A. Afzali-Kusha, “A Low Power Scan-Path Architecture”, The IEEE International Symposium on Circuits and Systems, pp. 5278-5281, Kobe, Japan, 2005.
• E. Atoofian and Z. Navabi, “A BIST Architecture for FPGA Look-Up Table Testing Reduces Reconfigurations”, Asian Test Symposium, pp.84-89, Nov. 16-19, Xi’an, China, 2003.
• E. Atoofian, S. Hatami, M. Alisafaee, Z. Navabi and A. Afzali-Kusha, “A New Low-Power Scan-Path Architecture”, 4th Workshop on RTL and High Level Testing, Nov.20-21, Xi’an, China, 2003.
• E. Atoofian and Z. Navabi, “A Low Power BIST Architecture for FPGA Look-Up Table Testing”, IFIP VLSI-SOC, pp. 394-397, Dec.1-3, Darmstadt, Germany, 2003.

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